Filling algorithms and analyses for layout density control
نویسندگان
چکیده
منابع مشابه
Filling algorithms and analyses for layout density control
In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density c...
متن کاملComments on "Filling algorithms and analyses for layout density control"
1209 wire choices are available, because only the look-up table needs to be reconstructed for different choices of wire sizes. The look-up table is constructed very efficiently since every buffer-to-buffer delay is computed incrementally and only once. In other words, as the number of wire sizes increases, the new method is able to gain reduction in delay without need of dramatically increasing...
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To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add ll geometries, either at the foundry or, for better convergence of performance veri cation ows, during layout synthesis [10]. This paper proposes a new min-variation objective for the synthesis ...
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Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing (CMP) which has varying e ects on device and interconnect features, depending on local layout characteristics. To reduce manufacturing variation due to CMP and to improve yield and performance predictability, the layout needs to be made uniform with respect to certain density criteria, by inserting \ l...
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Many graph optimization problems can be viewed as graph layout problems. A layout of a graph is a geometric arrangement of the vertices subject to given constraints. For example, the vertices of a graph can be arranged on a line or a circle, on a twoor three-dimensional lattice, etc. The goal is usually to place all the vertices so as to optimize some specified objective function. We develop co...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 1999
ISSN: 0278-0070
DOI: 10.1109/43.752928